As a technique of increasing the density of a memory without depending on lithography, a structure in which an OTP (OneTime-Programmable) element is sandwiched between multilayer interconnections, a structure in which a plurality of layers of NAND flash memories are formed by repeating epitaxial growth of a silicon film, and the like have, for example, been proposed. However, these structures are problematic because the number of times of lithography increases along with an increase in the number of stacked layers. As an alternative technique, a 3D-stacked vertical memory has been proposed.
In the 3D memory, cylindrical holes (memory holes) are formed at once in a plurality of electrodes stacked on a semiconductor substrate. A memory film is formed on the inner wall of each hole. A polysilicon film (silicon pillar) is then formed in each hole. This allows to form at once memory strings formed from a plurality of MONOS memory cells connected in series in the stacking direction.
In the MONOS memory cells, many defects caused by shortage in oxygen and dangling bonds exist in the interface between the Si (silicon) layer and the tunnel insulating film (for example, SiO2 film). These defects form interface states, resulting in a decrease in the carrier mobility or degradation of reliability.
To prevent this, a method has been proposed in which after Si layer formation, annealing is performed using an oxidizing gas to introduce oxygen into the interface between the Si layer and the tunnel insulating film. However, this annealing needs to be performed for a long time at a high temperature. Especially in the 3D memory, the annealing is done at the end of the MONOS memory cell manufacturing process. The annealing places a heavy thermal budget on the whole memory cells and consequently causes degradation of the memory cell characteristics and the like.